The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2003

Filed:

Jun. 04, 2002
Applicant:
Inventor:

Junya Kawamata, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

A semiconductor memory device is provided. The semiconductor memory device includes a primary memory area including a plurality of memory blocks arranged in rows and columns, the plurality of memory blocks including a predetermined memory block; a secondary memory area including a hidden memory block situated in the same column as the predetermined memory block; a decision circuit selecting one of a first mode for reading first data from the primary memory area and a second mode for reading second data from the secondary memory area, the decision circuit outputting a signal when the second mode and an address of the predetermined memory block are specified; a column decoder selecting a column corresponding to a column address inputted thereto; and a word-line decoder selecting a word line of the hidden memory block by boosting a word line of an adjacent memory block included in the primary memory area in response to the signal, the word-line decoder being included in the adjacent memory block, wherein the second data is read from the hidden memory block when the column decoder and the word-line decoder select the column corresponding to the hidden memory block and the word line of the hidden memory block respectively. According to the present invention, the semiconductor memory device enables efficient selection of an address of the secondary memory area with a simple circuit structure.


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