The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2003
Filed:
Mar. 27, 2000
Feng Yang, Plano, TX (US);
Techwell, INC, San Jose, CA (US);
Abstract
A sample rate converter that includes a number of selector elements coupled to a summing circuit. Each selector element receives a respective set of one or more processed data samples and provides one of the processed data samples. Each processed data sample is generated by delaying an input sample by zero or more clock cycles and scaling the sample by a particular scaling factor (e.g. 2 , where N is 0, 1, 2, and so on). The summing circuit receives and combines the processed data samples from the selector elements to generate an output sample. A delay and scaler circuit can receive the input sample and provide one set of processed data samples for each selector element. The delay and scaler circuit can include one or more delay elements coupled in series and to a scaling circuitry that scales selected ones of the input and delayed samples. The scaling can be implemented by simply bit-shifting the samples. The elements of the sample rate converter can be configured to implement a K-tap, P-phase interpolator.