The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2003
Filed:
Jun. 27, 2002
Michael Y. Zhang, Palo Alto, CA (US);
Tat Choi, Saratoga, CA (US);
Pericom Semiconductor Corp., San Jose, CA (US);
Abstract
A phase-locked loop (PLL) includes a final mixer on its output. The final mixer subtracts out a noise or error term from the PLL's output to reduce noise and jitter. A first mixer generates the error term by subtracting a feedback clock from the reference clock. This error term is near D.C. since the feedback and reference clocks are at the same frequency. When this error term is subtracted from the PLL output, a secondary maxima in the noise plot at the PLL's loop bandwidth is removed. A feedback counter receives the output of the voltage-controlled oscillator (VCO) before the final mixer. Outer-band noise created by the VCO is subtracted out by the final mixer, using the error term generated by the first mixer. The mixers reduce noise generated by the VCO or from other sources in the PLL.