The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2003

Filed:

May. 10, 2002
Applicant:
Inventor:

Yukio Iijima, Ikoma, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03B 2/100 ;
U.S. Cl.
CPC ...
H03B 2/100 ;
Abstract

A waveform generation apparatus comprises a delay circuit comprising i pieces of unit delay circuits connected in series, and providing i kinds of delay states by deriving signals from the respective unit delay circuits; k pieces of selection circuits each selecting one delay state from among the i kinds of delay states; a waveform generation circuit for generating n pieces of binary state signals in the same state, or generating n pieces of binary-state signals having a shape according to recording data supplied from the outside, on the basis of the signals having the i kinds of delay states; a transmission path for transmitting the n pieces of binary-state signals generated by the waveform generation circuit; a waveform synthesis circuit for generating a signal having multi-valued information from the n pieces of binary-state signals transmitted through the transmission path; a phase difference detection circuit for detecting phase differences among the n pieces of binary-state signals in the same state, when the n pieces of binary-state signals in the same state are transmitted through the transmission path; and an offset control circuit for controlling the k pieces of selection circuit on the basis of phase difference information from the phase difference detection circuit, and adding offset values to target delays, thereby to eliminate the phase differences among the signals in the transmission circuit.


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