The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2003
Filed:
Dec. 27, 2000
Applicant:
Inventors:
Takashi Aoyagi, Hitachinaka, JP;
Atsushi Ogishima, Tachikawa, JP;
Hirotaka Kobayashi, Kodaira, JP;
Yuji Hara, Akishima, JP;
Assignee:
Other;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/100 ;
U.S. Cl.
CPC ...
H01L 2/100 ;
Abstract
A semiconductor integrated circuit device including a plurality of holes in an interlayer insulating film beneath a bonding pad wherein a plug is buried in the respective holes and is made of the same conductive film (W/TiN/Ti) as a plug in a through-hole. Any wire as a second layer is not formed in a lower region of the bonding pad. The plug buried in the holes is connected only to the upper boding pad and is not connected to a lower wire.
Quick Actions:
Aoyagi, Takashi. (2003). Process for multilayer wiring connections and bonding pad adhesion to dielectric in a semiconductor integrated circuit device (U.S. Patent No. 6573170). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6573170
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile