The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6573156 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 03, 2003

Filed:

Dec. 13, 2001
Applicant:
Inventors:

David Xuan-Qi Wang, San Diego, CA (US);

Jason Yao, San Diego, CA (US);

Assignee:

OMM, Inc., San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/146 ;
U.S. Cl.
CPC ...
H01L 2/146 ;
Abstract

In certain implementations, a method for chip singulation is provided including etching a frontside dicing trench from a front side of a wafer, forming a temporary holding material, in the frontside dicing trench, etching a backside dicing trench from a back side of the wafer along the frontside dicing trench, removing the temporary holding material and releasing the chip from the wafer or an adjacent chip. Certain implementations may include etching through surface deposited layers on the front side of the wafer. Certain implementations may further include completely filling the frontside dicing trench with the temporary holding material and etching the backside dicing trench to the temporary holding material that is in the frontside dicing trench, such that removing the temporary holding material self-dices the wafer. Certain implementations may include surrounding MEMS structures with the temporary holding material so as to hold the structures during etching of the back side of the wafer. Some implementations may include providing a carrier wafer over the front side of the wafer. In certain implementations, the temporary holding material may be parylene, deposited by vapor deposition. In such implementations, the parylene may be removed by dry etching with an oxide plasma etch.


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Wang, David Xuan-Qi. (2003). Low defect method for die singulation and for structural support for handling thin film devices (U.S. Patent No. 6573156). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6573156

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