The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2003
Filed:
Mar. 02, 2001
Applicant:
Inventor:
Hiroki Narita, Tokyo, JP;
Assignee:
NEC Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
A circuit design apparatus of the present invention includes a first element which divides a circuit into a plurality of divided circuits and a second element which calculates individual constraint values of the divided circuits, respectively, using a constraint value of the circuit. A third element of the present invention optimizes each of the divided circuits based on the corresponding individual constraint values. A fourth element merges the divided circuits, which are optimized by the third element, into one circuit.
Quick Actions:
Narita, Hiroki. (2003). Circuit design apparatus and method thereof for optimizing a circuit (U.S. Patent No. 6571377). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6571377
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile