High speed clock synchronous semiconductor memory in which the column address strobe signal is varied in accordance with a clock signal

Abstract

The column address strobe signal (CAS) which is changed in cycles as many as a plurality of times that of a clock signal cycle is input to the memory block (MBK to MBKn). A plurality of serial data readout from the memory cell array ( ) and parallel/serial converted by a parallel/serial converter circuit ( ) in synchronism with a clock signal cycle are output for every cycle when the column address signal (CASADR) is changed. Parallel data input to the memory block and serial/parallel converted by a serial/parallel converter circuit ( ) in synchronism with the clock signal cycle are written in the memory cell array. In this way, the access specification that the column address strobe signal is varied once per n cycles of the clock signal allows for a more rapid memory operation.