The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2003
Filed:
May. 03, 1999
Applicant:
Inventors:
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 5/39 ;
U.S. Cl.
CPC ...
G09G 5/39 ;
Abstract
A line delay generator including a packetizing circuit, one port RAM and a RAM controller. The RAM controller provides the one port RAM with a write command to write packet data generated by the packetizing circuit, and with a read command to read any one or more packet data currently stored in the one port RAM, and output them as line delay data. The line delay generator can solve a problem involved in a conventional line delay generator in that because m (positive integer) two-port FIFOs must be connected in cascade to generate m line delay data, the FIFO memory becomes bulky.