High-performance high-density cmos sram cell

Abstract

A high-performance high-density CMOS SRAM cell (MC) having first and second cross-coupled inverters each defined by serially connected complementary MOS transistors (TA/TC; TB/TD) serially connected between V and circuit ground to form a first inverter with a first data node ( ) between the two transistors (TA/TC) of the first inverter, and, in a similar manner, to form a second inverter with a second data node ( ) between the two transistors (TB/TD) of the second inverter. The gates of transistors of each inverter are connected together and cross-coupled to the data node of the other inverter. An access transistor (TE) is connected between a bit line (BL) and the first data node ( ) to provide data access thereto. A diode (D) is connected between the data node of one of the inverters and the common gate connection of the other inverter to facilitate the “write one” operation. The diode (D) can be implemented in dual work function polysilicon topologies by selectively doping adjacent regions of the single gate level polysilicon with an appropriate polysilicon doping type and concentration for each transistor type to form a PN junction ( ) in the polysilicon ( ). A window or opening ( ) is formed in the silicide strapping layer ( ) to enable the PN junction ( ) operation.