The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2003

Filed:

Jul. 02, 1999
Applicant:
Inventor:

Makoto Furuhashi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/200 ; G06F 1/204 ;
U.S. Cl.
CPC ...
G06F 1/200 ; G06F 1/204 ;
Abstract

An information processing apparatus has a DRAM for storing at least predetermined data, a system bus to which the DRAM is connected, a CPU for controlling the DRAM, and a CPU bus to which the CPU is connected. The information processing apparatus also has an SRAM connected to the system bus and the CPU bus, for storing data transferred from the DRAM, an address counter for generating an address of the SRAM based on an initial value, and a DMA controller for controlling data transfer between the DRAM and the SRAM using the address generated by the address counter. At a certain time, the DMA controller outputs an address D next to an initial address in the DRAM via the system bus to the DRAM, reads data B from the address D , and outputs the data B via the system bus to the SRAM. At the same time, the address counter increments a stored address S into an address S , and outputs the address S to the SRAM, which stores the data B at the address S . Using the address generated on the basis of the initial value, data can efficiently be transferred between the system bus and the CPU bus in synchronism with clock cycles.


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