Loop cache memory and cache controller for pipelined microprocessors

Abstract

A microprocessor and method for operating this microprocessor are disclosed. The microprocessor contains multiple execution units that receive instructions from an instruction pipeline. A loop cache memory is connected in communication with the instruction pipeline, such that it may both store instructions from the instruction pipeline and issue instructions to be executed by the execution units. A loop cache controller controls instruction flow. In operation, the loop cache controller is preferably signaled by a software instruction to begin building a software pipelined loop of a specified size into the loop cache memory. The loop cache controller then begins accumulating instructions from the instruction pipeline into the loop cache memory; these instructions may also remain in the pipeline for execution. When the kernel of the software pipelined loop is built into the loop cache memory, the controller preferably stalls the instruction pipeline and executes the loop using the cached instructions. Upon loop completion, the instruction pipeline is resumed. The present invention reduces the code size required for software pipelined loops by building the loop kernel into the loop cache memory, thus eliminating repetitive instructions generally required to fill a software pipeline. The invention further allows power consumption to be reduced during loop execution as loop instructions need not be retrieved repetitively from standard cache or off-chip memory.