The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2003
Filed:
Jun. 05, 2001
Carl Taussig, Redwood, CA (US);
Richard Elder, Palo Alto, CA (US);
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Abstract
A memory circuit includes a cross-point memory array having first and second sets of transverse electrodes with respective memory elements formed at the crossing-points of the first and second set electrodes. Each of the memory elements is formed to include, in at least one of its binary states, a diode element. The memory circuit also includes an addressing circuit coupled to the memory array. The addressing circuit has a first set of address lines with first diode connections between the first set address lines and the first set memory array electrodes, with the first diode connections coupling each memory array electrode in the first set to a respective unique subset of the first set address lines. The addressing circuit also has a second set of address lines with second diode connections between the second set address lines and the second set memory array electrodes, with the second diode connections coupling each memory array electrode in the second set to a respective unique subset of the second set address lines. The first and second diode connections form a permuted diode logic circuit whereby application of predetermined voltages to selected subsets of the first and second address lines enables unique addressing of a single memory element in the array. By sensing the current in the address lines the binary state of the addressed memory element may be determined. Also, by application of a writing voltage to the selected subsets of address lines, the binary state of a memory element can be changed by substantially and permanently changing the resistance thereof.