Contents addressable memory with accelerated entry data shunting

Abstract

A contents addressable memory comprises: memory cells arranged in a matrix at positions where word lines extending along a row cross bit lines extending along a column; and search buses extending along the column and match lines extending along the row; and a comparison circuit, provided in each memory cell, comparing data in search bus and data stored in memory cell and outputting comparison result to the match line. Transfer units having a first transfer gate, a transfer cell for temporarily storing data from memory cell, and a second transfer gate are provided between a pair of memory cells arranged along the column. Data from one of pair of memory cells is stored in the transfer cell via first or second transfer gate, then that data stored in transfer cell is stored in other of pair of memory cells via the second or first transfer gate.