The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2003
Filed:
Sep. 27, 1999
Donald J. Curry, Menlo Park, CA (US);
David B. Kasle, Mountain View, CA (US);
James L. Ball, Santa Cruz, CA (US);
Todd W. Thayer, Mountain View, CA (US);
Stuart L. Claassen, Santa Clara, CA (US);
Xerox Corporation, Stamford, CT (US);
Abstract
A distributed digital imaging processing system having a number of processing units and circular FIFO buffers connected together using data transforming streams. Processing units read data from buffers using a transforming read streams. These read streams reorder the buffer data to form patches representing neighborhood pixels and may provide the same data multiple times. After processing a patch, a processing unit writes the resultant patch into a buffer using a transforming write stream which reorders the data into the storage format of the buffer. Several buffers can feed a single processor and one processor can feed several buffers. All the details of each data stream (buffer, current buffer location, patch size, access pattern) are stored in a table entry, along with a pointer to the data stream that it must follow in the buffer to avoid the hazards of reading and writing data out of order. In the case where a buffer has multiple read streams, requiring read streams to maintain a particular order reduces the work necessary to check for either a write or read hazard to comparing the location of a stream with it's leader. A single state machine computes from each table entry all addresses for all data transfers between the processors and buffers, and updates the table entry after each cycle. Since table entries define the streams which link processors to memory, communication paths between processors is completely under software control.