The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2003
Filed:
Oct. 29, 2001
Applicant:
Inventors:
David L. Schell, Fort Collins, CO (US);
Peter J. Windler, Fort Collins, CO (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11B 5/09 ;
U.S. Cl.
CPC ...
G11B 5/09 ;
Abstract
A circuit generally comprising a first circuit and a phase lock loop. The first circuit may be configured to (i) collect a plurality of samples per cycle during a plurality of cycles of an input signal and (ii) calculate a phase offset and a frequency offset for the input signal relative to a clock signal in response to the samples. The phase lock loop may be configured to (i) preset a phase error signal to the phase offset and a frequency error signal to the frequency offset and (ii) generate the clock signal in response to the phase error signal and the frequency error signal.