Base cell layout permitting rapid layout with minimum clock line capacitance on cmos standard-cell and gate-array integrated circuits

Abstract

A base cell for a gate array or standard cell integrated circuit design has N and P wells organized in checkerboard fashion, each well containing several P and N devices respectively. A first of the plurality of relatively deep P regions is adjacent to at least a first and a second of the plurality of relatively deep N regions. The first relatively deep N region is adjacent to the first relatively deep P region along a first edge of the first relatively deep N region, and to the second relatively deep P region along a second edge of the relatively deep N region. The first and second edges of the relatively deep N region are perpendicular. An array of the base cells therefore has a checkerboard pattern, unlike the striped pattern of typical gate array and standard cell designs. The array of the base cells is amenable to minimizing clock parasitic capacitance when clocked inverters, including the complimentary clocked inverters of latches, are laid out at vertexes of the checkerboard pattern.