Process for the fabrication of dual gate structures for cmos devices

Abstract

In accordance with the invention, a process for forming a dual gate structure for CMOS devices comprises the steps of a) providing a semiconductor workpiece including n-type and p-type regions and a gate dielectric region for a dual gate structure formed over the regions, b) forming over the gate dielectric region a thin layer of semiconductor doped to one type of conductivity, c) selectively removing the doped semiconductor overlying the workpiece region of like conductivity doping and d) forming a thin layer of semiconductor doped to the opposite kind of conductivity. The doped layers are then planarized as by chemical-mechanical polishing (CMP). An additional layer of undoped semiconductor can optionally be applied to bury the doped layers, and the device can be finished by coating with metal silicide in the usual fashion. This process can be completed with only one photolithography step, simplifying device fabrication by several operations.