The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 2003
Filed:
Oct. 23, 2001
Masahiro Sano, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
The present invention is a method that can simultaneously and reliably optimize the clock propagation delay time and clock skew of the entire semiconductor integrated circuit. For this reason, in the present invention, a clock-supplying element and a plurality of clock-receiving elements are first disposed. Then, a wiring path is determined while adjusting both a wired state and a buffer-inserting position from the clock-receiving elements toward the clock-supplying element. Such a method according to the present invention is employed, for example, in the layout of a semiconductor integrated circuit such as an integrated circuit, a large-scale integration, etc. Particularly, it is employed in the automatic layout of a clock distributing circuit.