System and method for efficient instruction prefetching based on loop periods

Abstract

The invention contemplates a system and method for efficient instruction prefetching based on the termination of loops. A computer system may be contemplated herein, wherein the computer system may include a semiconductor memory device, a cache memory device and a prefetch unit. The system may also include a memory bus to couple the semiconductor memory device to the prefetch unit. The system may further include a circuit coupled to the memory bus. The circuit may detect a branch instruction within the sequence of instructions, such that the branch instruction may target a loop construct. A circuit may also be contemplated herein. The circuit may include a detector coupled to detect a loop within a sequence of instructions. The circuit may also include one or more counting devices coupled to the detector. A first counting device may count a number of clock cycles associated with a set of instructions within a loop construct. A second counting device may count the number of clock cycles remaining in a loop during the last iteration of the loop. The circuit may further include a logic component coupled to the second counting device, such that the logic component may enable/disable the prefetch unit. A method may further be contemplated herein. The method may include detecting when a set of instructions within a last iteration of a loop may be encountered. The method may also include counting a plurality of clock cycles needed to fetch the set of instructions within the loop. The method may enable the prefetch unit when a remaining number of clock cycles substantially equals the number of clock cycles needed to access a memory device.