The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6563323 B1

PDF
Full Text
Expired
Date of Patent:
May. 13, 2003

Filed:

Jul. 26, 2002
Applicant:
Inventors:

Chizuru Inoshita, Tokyo, JP;

Kazuo Aoki, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 3/128 ; G06F 1/100 ;
U.S. Cl.
CPC ...
G01R 3/128 ; G06F 1/100 ;
Abstract

In a method of testing a semiconductor integrated circuit, an input signal is supplied to a logic circuit of the semiconductor integrated circuit. Current from a static power source passing through the semiconductor integrated circuit is repeatedly meansured while a logic state of the semiconductor integrated circuit is sequentially changed. Maximum and minimum currents are selected from the measured currents and an average current calculated from the measured currents. A determination is made that the semiconductor integrated circuit is defective when either of the difference between the average and maximum currents or the difference between the average and minimum currents exceeds a threshold value.


Find Patent Forward Citations

Inoshita, Chizuru. (2003). Method for testing a semiconductor integrated circuit (U.S. Patent No. 6563323). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6563323

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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