Multi-thread processing

Abstract

A multi-thread computer system comprising an array of thread units and associated sets of execution units. The thread units are designed to be interconnected in a one-dimensional array with other thread units of the array via respective multi-bit bi-directional communication paths for transferring threads and for relaying activity values between thread units. Each thread unit has a thread control unit. Each thread control unit has on its left side a first multi-bit input and a first multi-bit output, each connected to a first one of the bi-directional communication paths, and on its right side a second multi-bit input and a second multi-bit output, each connected to a second one of the bi-directional communication paths. Each thread control unit also has an activity sensor for determining the activity state of the thread unit as well as logic arranged to receive first and second input activity values from the first and second multi-bit inputs respectively, and an activity state signal from the activity sensor. The logic is configured to set the first and second output activity values to a maximum value when the thread unit is active and, when the thread unit is inactive, to set the first output activity value to a value one less than the second input activity value and to set the second output activity value to a value one less than the first input activity value. The thread unit also has a thread propagation controller responsive to the activity signals present at the first and second multi-bit inputs for controlling thread duplication and migration events. In further embodiments the thread units are interconnected in multi-dimensional arrays of various topologies.