Semiconductor device having scan test circuit that switches clock signal between shift mode and capture mode, and method of testing the semiconductor device

Abstract

In one of a digital circuit and a semiconductor device, each having a scan chain, a clock fed to a clock input terminal of a flipflop forming the scan chain is switched between during a shift mode and during a capture mode. The time interval from the last clock pulse of the clock signal selected during the shift mode to the first clock pulse of the clock signal selected during the capture mode is set to be shorter than the pulse interval (period) between adjacent pulses of the clock signal selected during the shift mode. In this arrangement, a low-speed tester operates at a substantially high speed, permitting scan-path testing to be carried out with low cost involved.