The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2003

Filed:

Mar. 04, 2002
Applicant:
Inventors:

Shigeru Atsumi, Tokyo, JP;

Hironori Banba, Tokyo, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 1/604 ;
U.S. Cl.
CPC ...
G11C 1/604 ;
Abstract

A nonvolatile semiconductor memory device includes a row decoder circuit having first and second N-channel MOS transistors and first and second P-channel MOS transistors which correspond to each of word lines. One end of a source-to-drain current path of the first N-channel MOS transistor is connected to the word line, and the other end thereof is connected to a corresponding one of output terminals of a predecoder circuit. One end of a source-to-drain current path of the second N-channel MOS transistor is connected to the word line, and the other end thereof is supplied with a voltage of OV or more in a data erase mode and is supplied with a low logical level signal in modes other than the data erase mode. A source-to-drain current path of the first P-channel MOS transistor is connected in parallel to the source-to-drain current path of the first N-channel MOS transistor, and a source-to-drain current path of the second P-channel MOS transistor is connected in parallel to the source-to-drain current path of the second N-channel MOS transistor.


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