The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 06, 2003
Filed:
Sep. 04, 2001
Neal W. Hollenbeck, Palatine, IL (US);
Lawrence Edwin Connell, Naperville, IL (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A single ended input differential output amplifier ( ) and integrated circuit including such an amplifier ( ). A pair of load resistors ( ) are connected between a supply voltage (V ) and differential outputs OUTP and OUTM. An inductor ( ) is connected between input RFIN and a source bias voltage V . A first field effect transistor (FET) ( ) is connected, drain to source, between load resistor ( ) at output OUTP and inductor ( ) at RFIN. A second FET ( ) is connected, drain to source, between the second load resistor ( ) at output OUTM and the source bias voltage V . A gate bias voltage V is connected to the gate of FET ( ) and through resistor ( ) to the gate of FET ( ). A coupling capacitor ( ) is connected between the input RFIN and the gate of FET ( ). The gate of FET ( ) may be connected to gate bias voltage V through a second gate bias resistor ( ) and a second coupling capacitor ( ) may couple the source of FET ( ) to the gate of FET ( ), thereby providing common mode rejection for noise, e.g., substrate noise, experienced at inductor ( ).