Multiplied clock generating circuit

Abstract

A multiplied clock generating circuit for generating and outputting an output clock signal that has a higher frequency than an input clock by a factor M is described. The multiplied clock generating circuit comprising: a frequency divider circuit which is configured to generate a feedback clock signal by dividing the output clock signal by a factor M; a phase comparator circuit which is configured to receive the input clock signal and the feedback clock signal as generated by the frequency divider circuit, to compare the phase of the input clock signal with the phase of the feedback clock signal and to output a phase displacement signal indicative of the phase relationship between the input clock signal and the feedback clock signal; a comparator which is configured to receive the phase displacement signal, to count the output clock signal within each cycle of the feedback clock signal while the phase displacement signal is indicative that there is a phase displacement between the feedback clock signal and the input clock signal, to compare the numbers as counted in successive cycles of the feedback clock signal, and to output a delay time adjustment signal on the basis of the result of the comparison; and an oscillator circuit which is capable of controlling the output clock signal in the clock period thereof by an increment(s) of a predetermined delay time on the basis of the delay time adjustment signal and outputting the output clock signal as controlled.