The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2003

Filed:

Feb. 11, 2002
Applicant:
Inventors:

Masahito Otsuki, Nagano, JP;

Seiji Momota, Nagano, JP;

Mitsuaki Kirisawa, Nagano, JP;

Takashi Yoshimura, Nagano, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18238 ;
U.S. Cl.
CPC ...
H01L 2/18238 ;
Abstract

A method for manufacturing a semiconductor device constituting an JGHT is provided that allows to manufacture the device using an inexpensive wafer and with high yields, and achieves low losses. Specifically, after an emitter electrode is formed, a reverse principal surface is polished to a specified thickness. The center line average height Ra of the polished surface is controlled to be not more than 1 &mgr;m, and the filtered center line waviness Wca is kept within 10 &mgr;m. The polished surface is selectively cleaned with an aqueous chemical solution to remove particles. To the cleaned surface, phosphorus ions arc implanted for forming a field-stop layer and boron ions are implanted for forming a collector layer. The wafer is then put into a diffusion furnace and annealed at a temperature from 300° C. to 550° C. to form a field-stop layer and a collector layer. Finally, a collector electrode is formed.


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