The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2003

Filed:

Feb. 11, 2000
Applicant:
Inventor:

Koichi Nishida, Tenri, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

The present invention relates to a scheduling method and apparatus for high-level synthesis of a circuit which is represented by an operation description. The method includes calculating a probability for each of a plurality of nodes included in a control flow graph to be assigned to a time step and calculating a sum of the probabilities for each time step. For each node having a scheduling candidate in a time step for which the sum of probabilities is maximum, an estimated value of an area of the circuit is calculated with the node having been temporarily assigned to the scheduling candidate and a combination of a node and a scheduling candidate for which the estimated value is maximum is retrieved. Finally, a list of scheduling candidates of the node in the combination is narrowed down by excluding the scheduling candidate in the combination from the list of scheduling candidates of the node in the combination.


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Nishida, Koichi. (2003). Scheduling method for high-level synthesis and recording medium (U.S. Patent No. 6557158). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6557158

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