Method of extracting timing characteristics of transistor circuits, storage medium storing timing characteristic library, lsi designing method, and gate extraction method

Abstract

A method of extracting timing characteristics from transistor circuit data of modularity design products (a module) such as a CPU core in which the extracted timing characteristics are used for the timing verification of a circuit including a module to be extracted and timing constraints when logical synthesis or timing-driven layout is made. Particularly, since conditions fit for a timing rule of the module are included in timing characteristics when timing verification is executed by simulation, verification free of pseudo error is enabled. Also, the configuration of a timing characteristic library, a storage medium storing it and an LSI designing method using the storage medium are provided.