The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2003

Filed:

May. 18, 1999
Applicant:
Inventor:

Richard C. Lyon, Boulder Creek, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G03F 7/20 ;
U.S. Cl.
CPC ...
G03F 7/20 ;
Abstract

The present invention provides a manufacturing environment ( ) for a wafer fab, and an SPDA data environment ( ) for acquiring processing parameters and metrology data of production runs. A computation environment ( ) processes the SPDA data to prepare delta graphs ( and ) of the present invention. These delta graphs are then analyzed in an analysis environment ( ). An MES environment ( ) evaluates the analysis and executes a process intervention if the results of the analysis indicate processing or product quality problems in the process run of the manufacturing environment ( ). Additionally, the invention provides for SPDA delta graphs of SPC control charts as well as SPC techniques utilizing process control limits based on delta graphs to identify, analyze and trouble-shoot semiconductor processing problems, in order to improve equipment reliability and wafer yield. The present invention also provides a process ( ) for computer integrated equipment time states including a service procedures module ( ) linked to preventive maintenance time states ( and ) and to a repair time state ( ).


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