Digital pll circuit and signal regeneration method

Abstract

An input data signal is digitally sampled by a data sampling section using an N-phase clock signal including N clock signals whose frequencies are almost the same as the bit rate of the input data signal and whose phases has been successively shifted by 1/N of the clock cycle, and thereby a parallel sample data signal including N sample data signals is obtained. An edge point detection operation section detects edge points in the N sample data signals in one cycle of an extracted clock signal and outputs an edge point operation output signal. A clock signal extraction section selects a clock signal from the N-phase clock signal based on the information of the edge point operation output signal and outputs the selected clock signal as the extracted clock signal. A delay section delays the N sample data signals of the parallel sample data signal and thereby outputs a parallel delayed sample data signal including N delayed sample data signals. A data regeneration section selects a delayed sample data signal from the N delayed sample data signals based on the information of the edge point operation output signal and outputs the selected delayed sample data signal as a regenerated data signal. Due to the delay by the delay section, extraction time of the digital PLL circuit can be decreased to 0 without enlarging the overhead in the input data signal.