The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 29, 2003
Filed:
Dec. 19, 2000
Applicant:
Inventor:
Jong-Hee Han, Ichon-shi, KR;
Assignee:
Hynix Semiconductor, Seoul, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract
A delay locked loop is used in a semiconductor memory device. The delay locked loop includes a controllable delay chain block for controlling a delay time of a clock signal coupled thereto, a comparison block for detecting the increase and decrease in the delay time by comparing a reference clock signal with a delayed clock signal generated from the controllable delay chain block, and an instant locking delay control block for controlling the increase and decrease in the delay time of the delay chain block in response to an output signal of the comparison block, the delayed clock signal and the reference clock signal.