The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2003

Filed:

Aug. 27, 2001
Applicant:
Inventors:

Mohamed Imam, Tempe, AZ (US);

Raj Nair, Chandler, AZ (US);

Mohammed Tanvir Quddus, Tempe, AZ (US);

Masaru Suzuki, Aizuwakamatsu, JP;

Takeshi Ishiguro, Aizuwakamatsu, JP;

Jefferson W. Hall, Phoenix, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/701 ; H01L 2/712 ; H01L 3/10392 ; H01L 2/362 ;
U.S. Cl.
CPC ...
H01L 2/701 ; H01L 2/712 ; H01L 3/10392 ; H01L 2/362 ;
Abstract

A semiconductor device ( ) is disclosed which can accommodate a negative voltage on its source using a P-type substrate ( ) which is connected to ground potential. A first embodiment illustrates a device which can handle high voltage applications as well as a negative voltage applied to the source. A drain contact region ( ) is recessed by a dimension (X) from a first insulated region ( ). The dimension (X) provides for an optimum distance for high voltage applications while avoiding lateral surface punch-through. A second embodiment illustrates a gate structure ( ) having a shape which surrounds a drain contact region ( ) and accommodates a high voltage application while also eliminating the lateral surface punch-through. The drain contact region ( ) is formed in a P-type region ( ) centered inside the gate structure ( ).


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