The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2003

Filed:

Nov. 22, 2000
Applicant:
Inventor:

Michael W. Dennen, Raleigh, NC (US);

Assignee:

Thunderbird Technologies, Inc., Research Triangle Park, NC (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/9784 ;
U.S. Cl.
CPC ...
H01L 2/9784 ;
Abstract

Field effect transistors include a semiconductor substrate of first conductivity type having a surface. A tub region of second conductivity type is in the semiconductor substrate at the surface and extends into the semiconductor substrate a first depth from the first surface. Spaced apart source and drain regions of the second conductivity type are included in the tub region of second conductivity type at the surface, to define single conductivity junctions of the second conductivity type with the tub region of second conductivity type. The spaced apart source and drain regions extend into the tub region a second depth that is less than the first depth. A trench is included in the tub region, between the spaced apart source and drain regions, and extending from the surface into the tub region to a third depth that is more than the second depth but is less than the first depth. An insulated gate electrode is included in the trench. Source and drain electrodes are provided on the surface that electrically contact the source and drain regions respectively. These field effect transistors may be fabricated by forming a tub region of second conductivity type in a semiconductor substrate of first conductivity type at a surface thereof, and extending into the semiconductor substrate a first depth from the surface. A source/drain region of the second conductivity type is formed in the tub region of second conductivity type at the surface, to define a single conductivity junction of the second conductivity type with the tub region of second conductivity type. The source/drain region extends into the tub region a second depth that is less than the first depth. A trench is formed in the source/drain region, to define spaced apart source and drain regions therefrom. The trench extends from the surface into the tub region a third depth that is more than the second depth but is less than the first depth. An insulated gate electrode is formed in the trench. Source and drain electrodes are formed on the surface that electrically contact the source and drain regions, respectively.


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