The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 29, 2003
Filed:
Mar. 21, 2001
Applicant:
Inventor:
Massud A. Aminpur, Dresden, DE;
Assignee:
Advanced Micro Devices, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/144 ;
Abstract
With standard DUV lithography technology it is not easy to achieve MOS transistor gates in sub-100 nm range. With the method of trim-etching in HI/O plasmas there is an opportunity to use the current lithography tools, to reduce the dimensions of the resist feature, and to achieve sub-100 nm MOS transistor gates for advanced devices. The method of trim-etching in HI/O plasmas delivers another factor to control the critical dimension of the MOS devices very accurately. Therefore, this invention helps to significantly reduce the total cost for manufacturing small MOS devices with a critical dimension in the sub-100 nm range.