The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2003

Filed:

Mar. 23, 1999
Applicant:
Inventor:

Shye-Lin Wu, Hsinchu, TW;

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ; H01L 2/976 ; H01L 2/994 ; H01L 3/162 ; H01L 3/1113 ;
U.S. Cl.
CPC ...
H01L 2/1336 ; H01L 2/976 ; H01L 2/994 ; H01L 3/162 ; H01L 3/1113 ;
Abstract

A method for fabricating MOSFETs with a recessed self-aligned silicide contact and extended source/drain junctions is described. A gate structure having a gate insulating layer, a first conductive layer and a first dielectric layer is formed on a substrate. A thermal oxide layer is formed on the substrate and on sidewalls of the first conductive layer. The first dielectric layer is removed. Extended source and drain junctions are formed in the substrate under a region covered by the first thermal oxide layer. Sidewall spacers are formed on the sidewalls of the gate structure to protect the extended source and drain junctions therebeneath from being silicided. The second thermal oxide layer is removed to form recessed regions on a substrate surface. A first metal layer is formed on the substrate after the first dielectric layer is removed. Source/drain regions under the recessed regions are formed.


Find Patent Forward Citations

Loading…