The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 29, 2003
Filed:
Dec. 14, 1999
Martin M. Fejer, Menlo Park, CA (US);
Gregory D. Miller, Foster City, CA (US);
Robert G. Batchko, Stanford, CA (US);
Robert L. Byer, Stanford, CA (US);
The Board of Trustees of the Leland Stanford Junior University, Stanford, CA (US);
Abstract
A method for fabricating periodically poled structures. The method produces an electric field within a ferroelectric substrate by applying a voltage waveform to an electrode structure disposed on a surface of the substrate. The waveform raises the electric field magnitude to a level substantially greater than that required to reverse domains within the substrate. The waveform then lowers the voltage such that the electric field has a value at which a domain wall velocity is most sensitive to changes in the field. The waveform maintains the electric field value until a current through the substrate drops substantially. The electric field is then lowered to a value below a level required to sustain domain wall motion, but greater than a level below which backswitching occurs. The electric field is then lowered to zero in such a way as to prevent backswitching. Alternatively, the electric field is maintained for a time t determined by t=x/v, where x is a domain wall half-width and v is a domain wall velocity. Subsequently, the waveforms lower the voltage to zero.