The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 22, 2003
Filed:
Feb. 10, 2000
Applicant:
Inventors:
Shiva P. Gowni, Santa Clara, CA (US);
Rakesh Mehrotra, Santa Clara, CA (US);
Assignee:
Cypress Semiconductor Corp., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
A circuit comprising a plurality of gates and a plurality of control circuits. The plurality of gates may each have an output connected to an input of a next gate of the plurality of gates. The plurality of control circuits may be connected to a second input of one or more gates of the plurality of gates. The plurality of control circuits may simulate switching.
Gowni, Shiva. (2003). Static timing analysis with simulations on critical path netlists generated by static timing analysis tools (U.S. Patent No. 6553549). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6553549
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile