Programmable array built-in self test method and system for arrays with imbedded logic

Abstract

The present invention discloses a method and system for testing imbedded logic arrays. An imbedded logic array is first tested for read/write functionality and then a test sequence is run to test the imbedded logic function. The method of the present invention writes a first data pattern to all addresses in an imbedded logic array. Next a second data pattern is written to a specific address followed by a read selecting all addresses concurrently. The output of the imbedded logic array, during this test, is the logic combination of the first data pattern and the second data pattern at the address where the second data pattern was written. By comparing the imbedded logic array output to an expected output the imbedded logic of the array is tested. The present invention anticipates imbedded logic arrays where the expected data output is not a previously written pattern. A programmable expect generator (PEG) is added that generates expected patterns of output for comparison to the actual outputs of an imbedded logic array. In this embodiment of the present invention the same programmable Array Built-In Self Test (PABIST) system used to test the read/write functionality may be used to facilitate testing of the imbedded logic function of an imbedded logic array.