The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 22, 2003

Filed:

Nov. 08, 1999
Applicant:
Inventor:

Philip George Shephard, III, Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 3/128 ; G06F 1/100 ;
U.S. Cl.
CPC ...
G01R 3/128 ; G06F 1/100 ;
Abstract

A method and apparatus for testing a plurality arrays on a processor with an on chip built in self test engine on the processor. A subset of the plurality arrays on the processor is selected for testing using a control mechanism to selectively enable testing of the subset. Data patterns from the on chip built in self test engine are sent to the plurality arrays on the processor. A response is received at the on chip built in self test engine from the plurality arrays. The response from the plurality arrays is compared to an expected response using the on chip built in self test engine.


Find Patent Forward Citations

Shephard, III, Philip. (2003). Method and apparatus for selectively enabling and disabling functions on a per array basis (U.S. Patent No. 6553525). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6553525

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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