The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 22, 2003
Filed:
Jun. 12, 2001
Michio Komoda, Tokyo, JP;
Sigeru Kuriyama, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
In cases where a delay time in a wire, which connects a first NAND placed on the upstream side and a second NAND placed on the downstream side, is calculated, there are a plurality of logical paths in the first NAND, and a parasitic capacitance of an output pin of the first NAND is determined for each logical path. Therefore, the parasitic capacitance corresponding to each logical path of the first NAND is separated from a fixed load model which indicates a sum of a load of the wire and a capacitance of an input pin of the second NAND, and the parasitic capacitance is added to the fixed load model in the calculation of the delay time. Accordingly, a load for the delay time calculation can be produced while precisely reflecting the parasitic capacitance changing with the logical path on the load production, and the delay time calculation can be performed with high accuracy.