Post metalization chem-mech polishing dielectric etch

Abstract

A method for etching an insulating layer without damage to the conducting layer and associated liner layer within the insulating layer. A dielectric layer is deposited on a semiconductor substrate and then patterned. A liner layer and a conducting layer are then deposited within the patterned dielectric. A passivating layer is deposited on top of the conducting layer after the conducting layer has been planarized through chemical-mechanical polishing while simultaneously etching the dielectric layer through a process that does not damage the underlying conducting and liner layers. The insulating layer is preferably a dielectric such as silicon dioxide and the liner layer is tantalum, tantalum nitride or a combination of the two. The passivating layer preferably consists of carbon and fluorine bound up in various chemical forms. The conducting layer preferably consists of copper. Recipes for simultaneously forming the passivating layer and etching the dielectric layer, and for removing the passivating layer without damaging the underlying conducting and liner layers are provided.