Method of designing semiconductor integrated circuit device, and apparatus for designing the same

Abstract

In a method of and an apparatus for designing a semiconductor integrated circuit device, which are capable of causing each waveform rounding to fall within a predetermined limit value without delay calculations at an early stage of the development of the semiconductor integrated circuit device, a wiring path resistance Rpath from an output terminal of a target circuit cell to a next-stage circuit cell and an allowable longest wiring resistance RtL drivable by the target circuit cell are compared. When Rpath is less than or equal to RtL (S YES), the sum Rtotal of resistances of wiring loads in a net and RtL are compared. If Rtotal is less than or equal to RtL (S YES), then the next-stage circuit cell is judged to be drivable within a predetermined waveform rounding limit value. When Rtotal is greater than RtL (S NO), an effective resistance Rw of each wiring load and an allowable longest wiring effective resistance RwL are compared. When Rw is less than or equal to RwL (S YES), the waveform rounding at the next-stage circuit cell is judged to fall within a predetermined limit value.