The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 15, 2003
Filed:
Oct. 01, 1999
Florin Balasa, Tustin, CA (US);
Koen Lampaert, Laguna Beach, CA (US);
Conexant Systems, Inc., Newport Beach, CA (US);
Abstract
An automated method for packing cells in the generation of an integrated circuit design layout that is especially useful for circuits having symmetry constraints, which is the case for most analog circuits, uses sequence pair encoding and simulated annealing. From the set of all cells needed to implement the circuit, subsets of the cells are defined that must exhibit symmetry. Symmetry constraints are defined for each subset and the cells are encoded as ordered sequence-pairs. To reduce the solution space, the initial sequence pair encoding is required to be symmetry-feasible and the annealer subspace is limited to symmetry-feasible sequence-pairs.