The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 15, 2003
Filed:
Mar. 22, 1999
John G McBride, Ft Collins, CO (US);
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Abstract
A method and apparatus for evaluating an integrated circuit design to determine the effective wire resistance at a receiver node of a receiver gate disposed in a network in the integrated circuit. The rules checker apparatus comprises a computer capable of being configured to execute a rules checker program which analyzes information relating to the integrated circuit to calculate the effective wire resistance at the receiver node. The rules checker of the present invention traverses a path from the output node of the driver gate to the receiver node of the receiver gate and recursively sums the values of the parasitic resistances encountered along the path to maintain a total resistance value. Once the rules checker determines that the receiver node has been reached, the rules checker determines that the total resistance value equals the effective wire resistance at the receiver node. The rules checker also is capable of determining whether or not a path being traversed is a false path, i.e., a path that does not lead to the receiver node. When the rules checker determines that a path being traversed does not lead to the receiver node, the total resistance value is set to 0 so that the parasitic resistances along a false path are not taken into account in calculating the effective wire resistance at the receiver node.