Hybrid multiple redundant computer system

Abstract

A hybrid multiple redundant computer system ( ) having at least three parallel operating processing units ( ) including input module ( ), central processor module ( ), and output module ( ) in each processing unit is disclosed. The central processor module ( ) is connected to the associated input module ( ) and connected to primary and secondary output circuits ( ) located in the associated output module ( ) and in the neighboring output module ( ) respectively. Each processing unit ( ) further includes a watchdog controller ( ) that monitors the associated central processor module ( ) and transfers an alarm signal ( ) to each output module ( ) in the event that a central processor module ( ) fails. Primary and secondary output circuits ( ) in each output module ( ) control an output voter network ( ) and perform selectable but different logical functions among output data of the respective central processor modules ( ) and alarm signals ( ) for providing no single point of failure within the output module ( ). If alarm signals ( ) are not activated, the system generates an output ( ) using two-of-three vote among output data produced by three central processor modules ( ). In the event that one or two central processor modules ( ) fail, the system is reconfigured to a two-of-two and to a one-of-one vote configuration respectively. Each central processor module ( ) in turn monitors the status of all of the system components and disables faulty outputs by opening a fault recovery switch ( ) in the respective output module ( ) allowing continued system operation in the face of as many as two faults within any system components.