Semiconductor memory device capable of performing a write operation 1 or 2 cycles after receiving a write command without a dead cycle

Abstract

The present invention relates to a semiconductor memory device capable of performing a write operation 1 or 2 cycles after receiving a write command without necessitating a dead cycle. The elimination of the dead cycle between read and write operations improves bus efficiency and thus, speed. The memory device of the present invention includes an address input control means for receiving an external write or read address and delaying the write address by either 1 or 2 cycles. A data input control means receives external write data and delays the write data by a first or second predetermined number of cycles according to the write mode. A data transmission control means transmits the delayed write data responsive to a predetermined set of input commands. The data input control means reads the data from a cell corresponding to the read address, provides the write data to a cell corresponding to the write address, and writes the transmitted delayed data into the cell corresponding to the write address.