The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 15, 2003

Filed:

Feb. 27, 2002
Applicant:
Inventors:

Yasuaki Hirano, Tenri, JP;

Shuichiro Kouchi, Tenri, JP;

Yoshihisa Sekiguchi, Tenri, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 1/600 ;
U.S. Cl.
CPC ...
G11C 1/600 ;
Abstract

A well voltage setting circuit has a P-MOS transistor for applying erase pulse, a first N-MOS transistor for applying a reference voltage Vss to a P-well in a shutdown sequence after erase pulse application, and a second N-MOS transistor for forcing the P-well to the reference voltage Vss during write and read. The first N-MOS transistor has a driving capacity set to about {fraction (1/50)} of that of the second N-MOS transistor, so that a time for forcing the P-well to the reference voltage Vss is long enough to prevent occurrence of local latch-up during erase.


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