Sample and hold circuit with compression and expansion

Abstract

An electronic circuit comprising a sample and hold circuit (S/H) for sampling and temporarily holding an input data signal (U , I ), comprising means (S; T ) for the sampling of a data voltage (U ) which corresponds to the input data signal (U , I ), a capacitive element (C ) for temporarily holding the sampled voltage (U ), and means (CPR) for compressing the voltage range of the data voltage (U ) which is to be sampled. The electronic circuit is further provided with expansion means (EXP) for converting the sampled voltage (U ) into a sampled output data signal (I ) in a manner such that it corresponds linearly to the input data signal (U , I ). This is achieved, for example, by using a first field effect transistor (T ) for the compression means (CPR) and a second field effect transistor (T ) for the expansion means (EXP). The gate-source voltage of the first field effect transistor (T ) forms the data voltage (U ) which is compressed since the drain-source current of the first field effect transistor (T ) is linear with respect to the input data signal (U , I ). The first (T ) and second (T ) field effect transistors in fact form a sample and hold current mirror. Thus, though the output current of the sample and hold current mirror is approximately linear with respect to the input current, the output current is a sampled version of the input current.