The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 15, 2003
Filed:
Feb. 08, 2000
Hans-Peter Zwicknagl, Stuttgart, DE;
Peter Baureis, Kürnach, DE;
Jan-Erik Müller, Ottobrunn, DE;
Infineon Technologies AG, Munich, DE;
Abstract
A power transistor cell includes an air bridge and a plurality of individual transistors. Each of the plurality of individual transistors has at least one separate connection contact. Each of the at least one separate connection contact of the plurality of individual transistors is thermally conductively connected to one another through the air bridge forming air bridge connections, which define a contact plane. A surface of the contact plane that contains each connection path between two of the air bridge connections defines a convex region. The air bridge is formed to have, in the contact plane, dimensions that exceed a smallest convex region containing all of the air bridge connections in all directions of the air bridge. Each of the plurality of power transistor cells can be respectively thermally conductively connected to one another through the air bridge to form a block of power transistor cells. The air bridge has a dimension that significantly exceeds the length of the contact fingers in the longitudinal direction of the contact fingers, so that components of the air bridge that are present at the sides of a row of contact fingers can be mounted on metallic connection surfaces or on the substrate surface by conductive contact pillars. The configuration provides good heat dissipation from the individual transistors.